Modeling the Transistor Chain Operation in CMOS Gates for Short Channel Devices

A detailed analysis of the transistor chain operation in CMOS gates is introduced. The chain is modeled by a transistor pair, according to the operating conditions of the structure. The system of differential equations for the derived chain model is solved and analytical expressions which accurately describe the temporal evolution of the output voltage are extracted. For the first time, a fully mathematical analysis without simplified step inputs and linear approximations of the output waveform, and without resistors replacing transistors, is presented. The width of the equivalent transistor that replaces all nonsaturated devices is efficiently calculated, eliminating previous inconsistencies in chain currents. A mapping algorithm for all possible input patterns to a scheme that can be handled analytically is also derived. The final results for the calculated response and the propagation delay of this structure are in excellent agreement with SPICE simulations.